Wednesday, January 16, 2013

Microprocessor and Embedded Hardware Interview Questions

9 comments:

  1. What are the different instructions provided by ARM which are used for performing atomic operations?

    Ans :: The LDREX and STREX instructions split the operation of atomically updating memory into two separate steps. Together, they provide atomic updates in conjunction with exclusive monitors that track exclusive memory accesses, see Exclusive monitors. Load-Exclusive and Store-Exclusive must only access memory regions marked as Normal.
    LDREX
    The LDREX instruction loads a word from memory, initializing the state of the exclusive monitor(s) to track the synchronization operation. For example, LDREX R1, [R0] performs a Load-Exclusive from the address in R0, places the value into R1 and updates the exclusive monitor(s).
    STREX
    The STREX instruction performs a conditional store of a word to memory. If the exclusive monitor(s) permit the store, the operation updates the memory location and returns the value 0 in the destination register, indicating that the operation succeeded. If the exclusive monitor(s) do not permit the store, the operation does not update the memory location and returns the value 1 in the destination register. This makes it possible to implement conditional execution paths based on the success or failure of the memory operation. For example, STREX R2, R1, [R0] performs a Store-Exclusive operation to the address in R0, conditionally storing the value from R1 and indicating success or failure in R2.
    Alternative exclusive access sizes
    The ARMv6K architecture introduced byte, halfword and doubleword variants of LDREX and STREX:
    LDREXB and STREXB
    LDREXH and STREXH
    LDREXD and STREXD.
    The ARMv7 architecture added these to the Thumb instruction set in the A and R profiles. ARMv7-M supports the byte and halfword but not the doubleword variants. ARMv6-M does not support exclusive accesses.
    The architecture requires that each Load-Exclusive instruction must be used only with the corresponding Store-Exclusive instruction, for example LDREXB must only be used with STREXB.

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  2. How are the arguments and system call number passed while executing SVC instruction (for enter kernel mode from user mode in Linux)?

    Ans. :
    Simply entering kernel-space with the help of a system call alone is not sufficient because there are multiple system calls, all of which enter the kernel in the same manner. Thus, the system call number must be passed into the kernel. On x86, the syscall number is fed to the kernel via the eax register. Before causing the trap into the kernel, user-space sticks in eax the number corresponding to the desired system call. The system call handler then reads the value from eax. Other architectures do something similar.

    The system_call() function checks the validity of the given system call number by comparing it to NR_syscalls. If it is larger than or equal to NR_syscalls, the function returns -ENOSYS. Otherwise, the specified system call is invoked:

    call *sys_call_table(,%eax,4)


    In addition to the system call number, most syscalls require that one or more parameters be passed to them. Somehow, user-space must relay the parameters to the kernel during the trap. The easiest way to do this is via the same means that the syscall number is passed: The parameters are stored in registers. On x86, the registers ebx, ecx, edx, esi, and edi contain, in order, the first five arguments. In the unlikely case of six or more arguments, a single register is used to hold a pointer to user-space where all the parameters are stored.

    The return value is sent to user-space also via register. On x86, it is written into the eax register.

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    Replies
    1. Refer: http://www.makelinux.com/books/lkd2/ch05lev1sec3

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  3. What are memory barriers?

    Ans.:
    Independent memory operations are effectively performed
    in random order, but this can be a problem for CPU-CPU interaction and for I/O.
    What is required is some way of intervening to instruct the compiler and the
    CPU to restrict the order.

    Memory barriers are such interventions. They impose a perceived partial
    ordering over the memory operations on either side of the barrier.

    Such enforcement is important because the CPUs and other devices in a system
    can use a variety of tricks to improve performance, including reordering,
    deferral and combination of memory operations; speculative loads; speculative
    branch prediction and various types of caching. Memory barriers are used to
    override or suppress these tricks, allowing the code to sanely control the
    interaction of multiple CPUs and/or devices.

    Refer: https://www.kernel.org/doc/Documentation/memory-barriers.txt

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  4. It's nice posting to embedded students to attend the interview .

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